As it is well known, the diffused use of multimedia applications and the expansion of these applications require a management of a greater and greater amount of data to be stored in the shortest time possible.
To fulfill this request non volatile memory devices are currently used, with memory structures for example of the Flash-Nor type, which show, in fact, the peculiarity of managing a big number of data, storing them quickly.
The architectures of the memory devices currently used comprise memory cells matrixes organized in rows or Word-lines intersected by columns or Bit-lines, each matrix being divided for example into partitions, which comprise a plurality of sectors, with each sector comprising a group of cells. The groups are adjacent to each other and each comprises a predetermined number of Word-lines and Bit-lines of cells.
In each matrix of memory cells, according to the metal arrangements present in the matrix itself, a group comprising a predetermined number of columns is selected by a plurality of first enable signals and by at least one further plurality of second enable signals in relation to the number of metals present.
A main advantage of the Flash-Nor memories resides in that a programming operation of the cells of a group of columns is managed, as a whole, inside the device, i.e. it occurs sequentially for all the cells belonging to the columns of the group according to a specific decoding.
FIG. 1 shows a programming method of a group of columns of a Flash-Nor memory device by means of a flow chart.
The programming method provides a programming cycle defined by a repetition of programming steps D and control steps C until all the memory cells of the group have reached a desired threshold.
The control steps C of the method comprise a verify step 1 “pumps in verify conditions” in which a plurality of pumps verify the content of the cells belonging to the columns of the group being programming, and operates by means of a cyclic step 2 “verify loop” analyzing, in sequence, all the cells of the columns.
The control steps C also comprise a comparison step 3, indicated as “pattern”, which allows to check if each cell of each column has reached a desired threshold. If the comparison step 3 gives a positive result (YES) the method ends (END) and a correct programming of all the cells of the group has occurred.
In case of negative result (NO) of the comparison step 3, the method provides a second comparison step 4, indicated in the flow chart as “over programmed”, which verifies the cells of the group by controlling that they are not over-programmed. If the step of second comparison 4 gives a positive result (YES) the method ends (END) and a programming error 9, “Fail program error”, is emitted, suitable for defining a failure of the programming.
Instead, in case of negative result (NO) of the step of second comparison 4 the cells of the group that during the verify step 1 have not reached the desired threshold, but that are however cells to be programmed, are subjected to the programming steps D.
The programming steps D comprise a pulse application step 5 during which a pulses sequence, of defined maximum voltage, is generated by a plurality of “pumps in pgm conditions” and applied to the cells of the group to be programmed by means of a second cyclic step 6 “pulse loop”.
The programming steps D of the method thus comprise a step of voltage increase 7, by means of a circuit “DAC Increment & Store”, which defines an increase of the voltage to be used in a successive pulses sequence.
A successive overflow verify step 8, “Dac overflow”, if positive (YES), ends the method (END) and a programming error 9 is generated for signaling a failure of the programming of the cells of the group.
If instead the overflow verify step 8 is negative (NO), the cells of the group are subjected to a new programming cycle and the above described method steps, of control C and of programming D, are repeated.
As highlighted, the programming method of a group of cells ends with the programming of all the memory cells according to a desired threshold, or the method ends with a failure of the programming when two possible events occur:                the pulses sequence reaches a maximum value of acceptable voltage, without however the cells of the group reach the desired threshold;        one or more cells of the group are over-programmed.        
The annexed FIG. 2 schematically and partially shows a device 11 of the known type with an architecture suitable for realizing in particular the cyclic application step 6 of the above described programming step D.
It is good to note that these devices 11 show a particularly long passage time of the voltages from the programming step to the verify step, then, for trying to decrease the number of voltage switches, increasing the performances, each programming step between two successive verify steps, is carried out passing all the cells of the columns of the group. In this way, a pulses sequence for each programming step will comprise a number of pulses equal to the ratio between the number of cells of the group and a maximum parallelism allowed by the device 11.
In the present treatment reference will be made, in a specific way, to a “programming per row”, i.e., a programming which provides to sequentially select and to program cells belonging to a same row or word line WL.
In particular then, for each group to be programmed, the cells under programming belong to a same row or word-line WL, selected in the usual way, and to columns sequentially selected by means of suitable select signals YN, Y0 generated by a decoder 12.
A currently used non volatile memory device architecture is shown in FIG. 2. The architecture shows a group 11 to be programmed which comprises a group of columns, of a matrix of memory cells, associated with a respective logic circuit 30. The logic circuit 30 is a portion of a global circuit structure associated with the entire matrix for the management of the programming of the cells.
Each logic circuit 30 comprises a High Voltage circuit HV connected to a P_pulse signal for the control of a program load PL which allows to carry out a pulse programming of suitable selected cells.
In the embodiment shown, a matrix of cells is considered with a number of metallizations equal to three, and in particular, a first level M1, lower, and a level M3 where respectively a plurality of columns or local bit-lines LBL and a plurality of global bit-lines GBL are defined, and a second level M2 where the rows or word-lines WL are defined.
In the example of FIG. 2, the global bit-lines GBL of the group to be programmed 11 are shown in the number of eight GBLi i=0, . . . 7 and the local bit-lines LBLij are 32 connected in groups of four, consecutive, to a global bit-line GBLi.
The global bit-lines GBLi i=0, . . . 7 are enabled by means of a first select signal YNi, generated by the decoder 12, which activates a corresponding first enable transistor Tg g=0, . . . 7 interposed between each global bit-line GBLi i=0, . . . 7 and a control line Lc shared by all the global bit lines GBLi.
For each global bit-line GBLi i=0, . . . 7 corresponding to the local bit-lines LBLij j=0 . . . 3 are enabled by a same second select signal YOj j=0 . . . 3, generated by the decoder 12, which activates a corresponding second enable transistor Tij i=0, . . . 7 j=0, . . . 3 interposed between each local bit-line LBLij and the corresponding global bit line GBLi.
It is good to note then how, in the present embodiment, a switch of the second select signal YOj occurs after a complete switch of the first signal YNi.
In the embodiment shown, the cells of the matrix are of the two bits per cell type. Similar considerations can be carried out for matrixes with multilevel cells.
The group to be programmed 11 further comprises a discharge circuit 33 with a discharge transistor 34 interposed between the control line Lc and a ground reference. A discharge signal YNS_DISCH controls the discharge transistor 34 and allows to discharge possible high voltages on a selected column at the end of the application of the programming pulse on the local bit-line LBLij which comprises the programmed cell.
The group 11 to be programmed also comprises a Sense Amplifiers SA which, suitably controlled, allows to read the programmed cells of the sector 10.
It is good to note that an architecture of these groups 11 to be programmed allows a programming parallelism which depends on the number of program loads PL, moreover, if these program loads PL are equal to the number of Sense Amplifiers SA, the same number of cells can be programmed and read simultaneously.
The logic 32 of the logic circuit 30 comprises a plurality of latches registers LT, which store the evolution of the programming of each successive cell at each programming pulse.
In the example shown, with the cells storing two bits, each cell is connected with a couple of latches registers LT and the cell is programmed only if both the latches registers LT reach desired values. Each couple of latches registers LT, relative to a cell, is connected to a combinatory network RC which has an output Up relative to the programming state of the cell itself: to be programmed or not to be programmed.
The number of couples of latches registers LT and thus the number of outputs Up is equal to the number of the cells contained in the group, i.e., Up p=0, . . . N.
The outputs Up p=0. . . N of the combinatory networks RC are connected to a multiplexer 17 and are tested, during each programming step, on the basis of an address signal ADD_WB, supplied by the decoder 21.
The outputs Up are, in a sequential way, brought to an output O1 of the multiplexer 17 and suitably control the circuitry High Voltage 31 and thus the program load PL.
The described device, although satisfactory under several points of view, shows however some drawbacks, in fact, each program load PL programs a defined group of columns and it is necessary to repeat the logic circuit 30 for each program load PL. This architecture is expensive in terms of area occupied by the device.
Moreover, in the devices with architecture of the so called multibanking type, wherein simultaneously there is the programming of a group of cells belonging to a partition and the reading of a group of cells belonging to another partition, the expense of occupied area is even greater.
In fact, in these devices, it is often avoided that the lines transporting high voltages, i.e., the programming voltages, often very noisy, interfere with circuits arranged for the reading of the cells themselves that, through interference, could modify the read value. Then, for avoiding these interferences between cells belonging to bit lines under programming and reading, it is necessary to dedicate, to each partition, all the high voltage circuitry necessary for reading and for programming a cell, in particular the program load PL. This implies a remarkable increase of the occupied area.
A further device of the known type which, in part, solves the above cited drawbacks, is schematically shown in FIG. 3.
The device shows an architecture similar to the previously described one, with a group 40 to be programmed which comprises a portion of a matrix of memory cells structured in rows WL and columns BL associated with a column decoder 21 suitable for selectively activating a column of the group.
The decoder 21 generates a first enable signal YNi, which sequentially activates a group of global bit lines GBLi, which, in the present example, are in the number of eight i=0, . . . , 7, and a second enable signal YOj which activates a determined associated local bit line LBLj. The local bit lines LBLij in the present example are in the number of four. Each first enable signal YNi i=0, . . . , 7 controls a respective access transistor Ti i=0, . . . , 7 connected between each global bit line GBLi i=0, . . . , 7 and a program load PL, shared by all the columns GBLi i=0, . . . , 7 of the group.
Also in this example the programming occurs per “row” and then the switch of the second select signals YOj occurs after the complete switch of the first select signals YNi.
Also in this embodiment the cells are of the two bit per cell type, similar considerations can be made for multilevel cells.
The group 40 to be programmed also comprises a discharge circuit 33 with a discharge transistor 34, interposed between each global bit line GBLi and a ground reference, controlled by a suitable discharge signal YNS_DISCH which allows to discharge possible high voltages present on each column of the group selected at the end of the application of the programming pulses sequence.
The second device shows a second circuit 45 suitable for controlling the program load PL for a pulses programming of the cell of the selected column of the group.
In the present embodiment, the second circuit 45 comprises a circuit portion 43, unique for the entire matrix, associated by means of a bus Data_bus with plural second portions 44 one for each program load PL, i.e., for each group 40 to be programmed.
Then bidirectional bus Data_bus circulates on the whole device.
The central portion 43 comprises a plurality of couples of Latches registers LT which store the evolution of the programming of the cells, successive to each programming pulses sequence.
Each couple of latches registers LT, relative to a cell, is connected to a combinatory network RC which has an output Up p=0, . . . , N which detects the programming state of the cell itself: to be programmed or not to be programmed.
The outputs Up p=0, . . . , N of the combinatory networks RC are connected to a multiplexer 41 and are tested during each programming step, on the basis of an address signal ADD_WB supplied by the decoder 21, and brought in a sequential way to an output O1 of the multiplexer 41.
The multiplexer 41 is connected to a logic gate 42 which is in turn enabled by an update signal Update_pgmloads for the connection by means of the bus Data_bus to a first latch register LTc of the second portion 44 which suitably controls a high Voltage circuitry 31 and then the program load PL.
A programming cycle of the second device is partially shown in FIG. 4 where the waveforms are shown of the signals used during a programming step of two cells of a same selected row WLc and belonging to two global consecutive bit lines alternatively activated by the first select signal YNi, in particular YN3 and YN4. Moreover, these cells to be programmed belong to a local bit line LBLij, associated respectively with the global bit line GBL3 and GBL4, activated by a same second select signal YOj.
The programming provides a select and discharge step H1 where the discharge signal YNS_DISCH is activated, i.e., in the specific case brought to high logic level, by discharging the possible high voltage present in the column with the just programmed cell and, in the specific case, it will be the column activated by the first select signal YN2.
The step H1 provides the deactivation of the discharge signal Yns_disch there is a switch of the first select signal YNi by activating in particular YN3 which activating the transistor enables the global bit-line GBL3.
The programming thus provides with a preparation step H2, updating the first latch register LTc with the information if the selected cell must be programmed or not. In particular, during this step H2 the update signal Update_Pgmloads enables the logic gate 42 with the data transfer, by means of the bus Data_bus, from the output O1 of the multiplexer 41 to the first latch register LTc.
Finally, by means of a storage step H3, an impulsive signal P_PULSE is activated, i.e., brought to a high logic value, and the pulse programming goes on by means of the program loads PL of the cell of the local bit line LBL3j activated by the second select signal YOj and associated with the selected global bit line GBL3.
Subsequently to the storage step H3 it is necessary to arrange a time sufficiently long for discharging the high voltage accumulated on the just pulsed column, bringing the discharge signal YNS_DISCH which enables the discharge transistor 34 of the discharge circuit 33 to a high logic level.
The architecture of the second device allows to reduce the memory area occupied by the second circuit 45, in fact, the second portion 44 is repeated for each program load PL, while the central portion 43, which occupies a greater space in memory, is unique for the whole device.
The second device shown, although meeting the required needs of reducing the occupied area, shows however some drawbacks linked to the duration of the programming cycle, which remains quite high.
In fact, the discharge step H1 needs an execution time in the order of some tens of nanoseconds while the preparation step H2 needs an update time of the program load usually higher than the hundred of nanoseconds, value which depends on the parallelism of the communication bus and on the transfer speed. Then, their contribution-sum is extremely relevant and non negligible already in the presence of a programming pulse of the duration of a microsecond.